View A5974ADTR_8328208.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

april 2011 doc id 018762 rev 1 1/49 49 a5974ad up to 2 a step-down switching regulator for automotive applications features qualified following the aec-q100 requirements (see ppap for more details) 2 a dc output current operating input voltage from 4 v to 36 v 3.3 v / (2%) reference voltage output voltage adjustable from 1.235 v to 35 v low dropout op eration: 100% duty cycle 500 khz internally fixed frequency voltage feed-forward zero load current operation internal current limiting inhibit for zero current consumption synchronization protection against feedback disconnection thermal shutdown application dedicated to automotive applications description the a5974ad is a step-down monolithic power switching regulator with a minimum switch current limit of 2.5 a, it is therefore able to deliver up to 2 a dc current to the load depending on the application conditions. the output voltage can be set from 1.235 v to 35 v. the high current level is also achieved thanks to a hsop8 package with exposed frame, that allows to reduce the r thj-a down to approximately 40 c/w. the device uses an internal p-channel dmos transistor (with a typical r ds(on) of 250 m ) as switching element to minimize the size of the external components. an internal oscillator fixe s the switching frequency at 500 khz. having a minimum input voltage of only 4 v, it fits automoti ve applications requiring device operation even in cold crank conditions. pulse-by-pulse current limit with the internal frequency modulation offers an effective constant current short-circuit protection. hsop8 - exposed pad figure 1. application schematic !-v smallsignal po werplane 6 4/6 6/54 6## 62%& %8 0! $ ).( #/-0 '.$ &" 39.# 5 !!$ 2 + + 40 '.$ 40 6). # u& 6 $ 3403,5 40 '.$ 40 6/54 # u& # n& # p 2 + 2 + , u( # n& 6 www.st.com
contents a5974ad 2/49 doc id 018762 rev 1 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 datasheet parameters over the temperature range . . . . . . . . . . . . . . . 10 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6 pwm comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.7 inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 lc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 pwm comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
a5974ad contents doc id 018762 rev 1 3/49 8.1 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3.1 thermal resistance r thj-a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3.2 thermal impedance z thj-a (t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.5 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.6 positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.7 negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.8 floating boost current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.9 synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.10 compensation network with mlcc at the ou tput . . . . . . . . . . . . . . . . . . . 40 8.11 external soft-start network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
list of tables a5974ad 4/49 doc id 018762 rev 1 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. list of ceramic capacitors for the a5974ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10. hsop8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 11. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
a5974ad list of figures doc id 018762 rev 1 5/49 list of figures figure 1. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. current limitation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. driving circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. error amplifier equivalent circuit and compensation network . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. power losses estimation (v in = 5 v, f sw = 500 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16. power losses estimation (v in = 12 v, f sw = 500 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17. measurement of the thermal impedance of the demonstration board . . . . . . . . . . . . . . . . 31 figure 18. short-circuit current v in = 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. short-circuit current v in = 24 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 20. short-circuit current v in = 36 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21. demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 22. pcb layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 23. pcb layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 24. pcb layout (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 25. positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 26. negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 27. floating boost topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 28. 350 ma led boost current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 29. synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 30. mlcc compensation network circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 figure 31. soft-start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 32. line regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 33. shutdown current vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 34. output voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 35. junction temperature vs. output current (v in = 5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 36. junction temperature vs. output current (v in = 12 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 37. efficiency vs. output current (v in = 5 v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 38. efficiency vs. output current (v in = 12 v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 39. package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
pin settings a5974ad 6/49 doc id 018762 rev 1 1 pin settings 1.1 pin connection figure 2. pin connection (top view) 1.2 pin description !-v table 1. pin description n pin description 1 out regulator output. 2 synch master/slave synchronization. 3inh a logical signal (active high) disables the device. if inh is not used, the pin must be grounded. when it is open, an internal pull-up disable the device. 4 comp e/a output for frequency compensation. 5fb feedback input. connecting directly to this pin results in an output voltage of 1.23 v. an external resist ive divider is required for higher output voltages. 6v ref 3.3 v v ref . no cap is requested for stability. 7 gnd ground. 8v cc unregulated dc input voltage.
a5974ad electrical data doc id 018762 rev 1 7/49 2 electrical data 2.1 maximum ratings 2.2 thermal data table 2. absolute maximum ratings symbol parameter value unit v 8 input voltage 40 v v 1 out pin dc voltage out pin peak voltage at t = 0.1 s -1 to 40 -5 to 40 v v i 1 maximum output current int. limit. v 4 , v 5 analog pins 4 v v 3 inh -0.3 to v cc v v 2 synch -0.3 to 4 v p tot power dissipation at t a 60 c 2.25 w t j operating junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r thj-a maximum thermal resistan ce junction-ambient 40 (1) 1. package mounted on demonstration board. c/w
electrical characteristics a5974ad 8/49 doc id 018762 rev 1 3 electrical characteristics t j = -40 c to 125 c, v cc = 12 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test condition min. typ. max. unit v cc operating input voltage range v 0 = 1.235 v; i 0 = 2 a 4 36 v r ds(on) mosfet on- resistance 0.250 0.5 i l maximum limiting current v cc = 5 v 2.5 3.0 3.5 a f sw switching frequency 425 500 575 khz duty cycle 0 100 % dynamic characteristics (see test circuit) v 5 voltage feedback 4.4 v < v cc < 36 v, 20 ma < i 0 < 2 a 1.198 1.235 1.272 v dc characteristics i qop total operating quiescent current 57ma i q quiescent current duty cycle = 0; v fb = 1.5 v 2.7 ma i qst-by total standby quiescent current v inh > 2.2 v 50 100 a v cc = 36 v; v inh > 2.2 v 50 100 a inhibit inh threshold voltage device on 0.8 v device off 2.2 v error amplifier v oh high level output voltage v fb = 1 v 3.5 v v ol low level output voltage v fb = 1.5 v 0.4 v i o source source output current v comp = 1.9 v; v fb = 1 v 190 300 a i o sink sink output current v comp = 1.9 v; v fb = 1.5 v 1 1.5 ma i b source bias current 2.5 4 a dc open loop gain r l = 50 65 db gm transconductance i comp = -0.1 ma to 0.1 ma; v comp = 1.9 v 2.3 ms synch function
a5974ad electrical characteristics doc id 018762 rev 1 9/49 high input voltage v cc = 4.4 to 36 v 2.5 v ref v low input voltage v cc = 4.4 to 36 v 0.74 v slave synch current (1) v synch = 0.74 v v synch = 2.33 v 0.11 0.21 0.25 0.45 ma master output amplitude i source = 3 ma 2.75 3 v output pulse width no load, v synch = 1.65 v 0.20 0.35 s reference section reference voltage i ref = 0 to 5 ma v cc = 4.4 v to 36 v 3.2 3.3 3.399 v line regulation i ref = 0 ma v cc = 4.4 v to 36 v 510mv load regulation i ref = 0 ma 8 15 mv short-circuit current 5 18 35 ma 1. guaranteed by design. table 4. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
datasheet parameters over the temperature range a5974ad 10/49 doc id 018762 rev 1 4 datasheet parameters o ver the temperature range 100% of the population in the production flow is tested at three different ambient temperatures (-40 c, +25 c, and +125 c) to guarantee the datasheet parameters inside the junction temperature range (-40 c, +125 c). the device operation is guaranteed when the junction temperature is inside the (-40 c; +150 c) temperature range. the user can esti mate the silicon temperature increase with respect to the ambient temperature evaluating the internal power losses generated during device operation (please refer to section 2.2 ). however, the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the t shtdwn (+150 c10 c) temperature. all the datasheet parameters can be guaranteed to a maximum junction temperature of +125 c, to avoid triggering the thermal shutdown protection during the testing phase due to self heating.
a5974ad functional description doc id 018762 rev 1 11/49 5 functional description the main internal blocks are shown in the device block diagram in figure 3 . they are: a voltage regulator supplying the internal circuitry. from this regulator, a 3.3 v reference voltage is externally available. a voltage monitor circuit which checks the input and the internal voltages. a fully integrated sawt ooth oscillator with a frequency of 500 khz 15%, including also the voltage feed-forward function and an input/output synchronization pin. two embedded current limitation circuits which control the current that flows through the power switch. the pulse-by-pulse current limit forces the power switch off cycle- by-cycle, if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle. a transconductance error amplifier. a pulse width modulator (pwm) comparator and the relative logic circuitry necessary to drive the internal power. a high side driver for the internal p-mos switch. an inhibit block for standby operation. a circuit to implement the thermal protection function figure 3. block diagram !-v
functional description a5974ad 12/49 doc id 018762 rev 1 5.1 power supply and voltage reference the internal regulator circuit (shown in figure 4 ) consists of a start-up circuit, an internal voltage pre-regulator, the bandgap voltage reference and the bias block that provides current to all the blocks. the starter supplies the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). the pre-regulator block supplies the bandgap cell with a pre-regulated voltage, v reg , that has a very low supply voltage noise sensitivity. 5.2 voltage monitor an internal block continuously senses the v cc , v ref and v bg . if the voltages go higher than their thresholds, the regulator begins operat ing. there is also a hysteresis on the v cc (uvlo). figure 4. internal circuit 5.3 oscillator and synchronization figure 5 shows the block diagram of the oscillator circuit. the clock generator provides the switching frequen cy of the device, which is internally fixed at 500 khz. the frequency shifter block acts to reduce the switching frequency in case of strong overcurrent or short-circuit. the clock signal is then used in the internal logic circuitry and is the input of the ramp generator and synchronizer blocks. the ramp generator circuit provides the sawtooth signal, used for pwm control and the internal voltage feed-forward, while the synchronizer circuit generates the synchronization signal. the device also has a synchronization pin which can wo rk both as master and slave. beating frequency noise is an issue when more than one voltage rail is on the same board. a simple way to avoid this issue is to operate all the regulators at the same switching frequency. the synchronization feature, of a set of the a5974ad, is simply obtained by connecting together their synch pins. the device with the highest switching frequency is the master, !-v
a5974ad functional description doc id 018762 rev 1 13/49 which provides the synchronization signal to the others. therefore the synch is an i/o pin to deliver or recognize a frequency signal. the synchronization circuitry is powered by the internal reference (v ref ), so a small filtering capacitor ( 100 nf) connected between the v ref pin and the signal ground of the master device is recommended for its proper operation. however, when a set of synchronized devices populates a board, it is not possible to know in advance the one working as master, so the filtering capacitor must be designed for a whole set of devices. when one or more devices are synchronized to an external signal, its amplitude must be in compliance with specifications given in ta b l e 4 . the frequency of the synchronization signal must be, at a minimum, higher than the maximum guaranteed natural switching frequency of the device (275 khz, see ta bl e 4 ) while the duty cycle of the syn chronization signal can vary from approximately 10% to 90%. the small capacitor under the v ref pin is required for this operation. figure 5. oscillator circuit block diagram !-v
functional description a5974ad 14/49 doc id 018762 rev 1 figure 6. synchronization example 5.4 current protection the a5974ad features two types of current limit protection; pulse-by-pulse and frequency foldback. the schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in figure 7 . the output power pdmos transistor is split into two parallel pdmos transistors. the smallest one includes a resistor in series, r sense . the current is sensed through r sense and, if it reaches the threshold, the mirror becomes unbalanced and the pdmos is switched off until the next falling ed ge of the internal clock pulse. due to this reduction of the on time, the output voltage decreases. as the minimum switch-on time necessary to sense the current, in order to avoid a false overcurren t signal, is too short to obtain a sufficiently low duty cycle at 500 khz (see section 8.4 ), the output current in strong overcurrent or short-circuit conditions may not be properly limited. for this reason, the switching frequency is also reduced, therefore keeping the inductor current under its maximum threshold. the frequency shifter ( figure 5 ) functions based on the feedback voltage. as the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also. !-v 287 *1 ' &2 03 )% 66,1+ $' 6< 1&+ 287 *1' &203 )% 66,1+ $' 6<1&+ 287 *1 ' &203 )% 66,1+ $' 6<1&+ 287 *1 ' &2 03 )% 66,1+ $' 6< 1&+ $' $' $' $' $' $' 287 $' $' !!$ !!$ !!$ !!$
a5974ad functional description doc id 018762 rev 1 15/49 figure 7. current limitation circuitry 5.5 error amplifier the voltage error amplifier is the core of the loop regulation. it is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 v), while the inverting input (fb) is connected to the external divider or directly to the output voltage. the output (comp) is connected to the external compensation network. the uncompensated error amplifier has the following characteristics: the error amplifier out put is compared to the oscillato r sawtooth to perform pwm control. 5.6 pwm comparator and power stage this block compares the oscillator sawtooth and the error amplifier output signals to generate the pwm signal for the driving stage. the power stage is a highly critical block, as it functions to guarantee a correct turn-on and turn-off of the pdmos. the turn-on of the power element, or more accurately, the rise time of the current at turn-on, is a very critical parameter. at the first approach, it appears that the faster the rise time, the lower the turn-on losses. !-v $2)6%2 ./4 ! 07- 6## /54 !! ) , 23%.3% ) /&& ) ) 24( ! table 5. uncompensated error amplifier characteristics description values transconductance 2300 s low frequency gain 65 db minimum sink/source voltage 1500 a/300 a output voltage swing 0.4 v/3.65 v input bias current 2.5 a
functional description a5974ad 16/49 doc id 018762 rev 1 however, there is a limit introduced by the recovery time of the recirculation diode. in fact, when the current of the power element is equal to the inductor current, the diode turns off and the drain of the power is able to go high. but, during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for numerous problems: spikes on the device supply voltage that c ause oscillations (and th erefore noise) due to the board parasites. turn-on overcurrent leads to a decrease in the efficiency and system reliability. major emi problems. shorter free-wheeling diode life. the fall time of the current during turn-off is also critical, as it produces voltage spikes (due to the parasitic elements of the board) that increase the voltage drop across the pdmos. in order to minimize these problems, a new driv ing circuit topology has been used (the block diagram is shown in figure 8 ). the basic idea is to change the current levels used to turn the power switch on and off, based on the pdmos and the gate clamp status. this circuitry allows the power switch to be turned off and on quickly and addresses the free-wheeling diode recovery time problem. the gate clamp is necessary to ensure that v gs of the internal switch does not go higher than v gsmax . the on/off control block protects against any cross conduction between the supply line and ground. figure 8. driving circuitry !-v 6gs max '!4% 34/0 $2)6% $2!). /&& /. 0$-/3 6/54 $2!). 6## ) ,/!$ # %32 ) /&& ) /. /./&& #/.42/, #,!-0 ,
a5974ad functional description doc id 018762 rev 1 17/49 5.7 inhibit function the inhibit feature is used to put the device in standby mode. with the inh pin higher than 2.2 v, the device is disabled and the power consumption is reduced to less than 100 a. with the inh pin lower than 0.8 v, the device is enabled. if the inh pin is left floating, an internal pull-up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. the pin is also v cc compatible. 5.8 thermal shutdown the shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (15010 c). the sensing element of the chip is very close to the pdmos area, ensuring fast and accurate temperature detection. a hysteresis of approximately 20 c keeps the device from turning on and off continuously.
additional features and protection a5974ad 18/49 doc id 018762 rev 1 6 additional features and protection 6.1 feedback disconnection if the feedback is disconnected, the duty c ycle increases towards the maximum allowed value, bringing the output voltage close to the input supply. this condition could destroy the load. to avoid this hazardous condition, the device is turned off if the feedback pin is left floating. 6.2 output overvoltage protection overvoltage protection, or ovp, is achieved by using an internal comparator connected to the feedback, which turns off the power stage when the ovp threshold is reached. this threshold is typically 30% higher than the feedback voltage. when a voltage divider is required to adjust the output voltage ( figure 18 ), the ovp intervention is set at: equation 1 where r 1 is the resistor connected between the output voltage and the feedback pin, and r 2 is between the feedback pin and ground. 6.3 zero load due to the fact that the internal power is a pdmos, no bootstrap capacitor is required and so the device works properly even with no load at the output. in this case it works in burst mode, with a random burst repetition rate. v ovp 1.3 r 1 r 2 + r 2 -------------------- v fb ?? =
a5974ad closing the loop doc id 018762 rev 1 19/49 7 closing the loop figure 9. block diagram of the loop !-v
closing the loop a5974ad 20/49 doc id 018762 rev 1 7.1 error amplifier and compensation network the output lc filter of a step-down converter contributes with 180-degree phase shift in the control loop. for this reason a compensation network between the comp pin and ground is added. the simplest compensation network, together with the equivalent circuit of the error amplifier, are shown in figure 10 . r c and c c introduce a pole and a zero in the open loop gain. cp does not significantly affect system stability but it is useful to reduce the noise of the comp pin. the transfer function of the error amplifier and its compensation network is: equation 2 where a vo = g m r o figure 10. error amplifier equivalent circuit and compensation network the poles of this transfer function are (if c c >> c 0 +c p ): equation 3 equation 4 a 0 s () a v0 1s + r c c c ?? () ? s 2 r 0 c 0 c p + () r c c c sr 0 c c ? r 0 c 0 c p + () r c c c ? + ? + () 1 + ? + ?? ?? ------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------- = !-v # 0 2 # # # &" #/-0 ? 6 2 - ' m ? 6 6 %! 2 # # # # 0 # p& f p1 1 2 r 0 c c ?? ? --------------------------------- - = f p2 1 2 r c c 0 c p + () ?? ? ---------------------------------------------------- =
a5974ad closing the loop doc id 018762 rev 1 21/49 whereas the zero is defined as: equation 5 f p1 is the low frequency which sets the bandwidth, while the zero f z1 is usually put near to the frequency of the double pole of the lc filter (see below). f p2 is usually at a very high frequency. 7.2 lc filter the transfer function of the lc filter is given by: equation 6 where r load is defined as the ratio between v out and i out . if r load >>esr, the previous expression of a lc can be simplified and becomes: equation 7 the zero of this transfer function is given by: equation 8 f 0 is the zero introduced by the esr of the output capacitor and it is very important to increase the phase margin of the loop. the poles of the transfer function can be calculated through the following expression: equation 9 in the denominator of a lc the typical second order system equation can be recognized: equation 10 if the damping coefficient is very close to zero, the roots of the equation become a double root whose value is n . similarly for a lc the poles can usually be defined as a double pole whose value is: equation 11 f z1 1 2 r c c c ?? ? --------------------------------- = a lc s () r load 1esrc out s ?? + () ? s 2 lc out esr r load + () sesrc out r load l + ?? () r load + ? + ?? ? ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------- - = a lc s () 1esrc out s ?? + lc out s 2 esr c out s1 + ?? + ?? ----------------------------------------------------------------------------------------- = f o 1 2 esr c out ?? ? ----------------------------------------------- - = f plc1 2 , esr c out esr c out ? () 2 4lc out ?? () ? ? ? 2lc out ?? ------------------------------------------------------------------------------------------------------------------------------- -------------- - = s 2 2 ? n s 2 n + ?? ? + f plc 1 2 ? lc out ? ? ------------------------------------------- - =
closing the loop a5974ad 22/49 doc id 018762 rev 1 7.3 pwm comparator the pwm gain is given by the following formula: equation 12 where v oscmax is the maximum value of a sawtooth waveform and v oscmin is the minimum value. a voltage feed-forward is implemented to ensure a constant gpwm. this is obtained by generating a sawtooth waveform directly proportional to the input voltage v cc . equation 13 where k is equal to 0.038. therefore the pwm gain is also equal to: equation 14 this means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, therefore ensuring a better line regulation and line transient response. in summary, the open loop gain can be expressed as: equation 15 example: considering r c = 4.7 k , c c = 22 nf and c p = 150 pf, the poles and zeroes of a 0 are: f p1 = 9 hz f p2 = 220 khz f z1 = 1.6 khz if l = 12 h, c out = 330 f and esr = 25 m , the poles and zeroes of a lc become: f plc = 2.5 khz f zesr = 20 khz f 0 = 44 khz finally r 1 = 5.6 k and r 2 = 3.3 k . the gain and phase bode diagrams are plotted respectively in figure 11 and figure 12 . g pwm s () v cc v oscmax v oscmin ? () ------------------------------------------------------------- = v oscmax v oscmin ? kv cc ? = g pwm s () 1 k --- - const == gs () g pwm s () r 2 r 1 r 2 + -------------------- a o s () a lc ??? ?? ?? s () =
a5974ad closing the loop doc id 018762 rev 1 23/49 figure 11. module plot figure 12. phase plot the cut-off frequency and the phase margin are: equation 16 f c 38khz = phase margin = 52
application information a5974ad 24/49 doc id 018762 rev 1 8 application information 8.1 component selection input capacitor the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. as step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. the input capacitor has to absorb all this switching current, which can be up to the load current divided by two (worst case, with duty cycle of 50%). for this reason, the quality of these capacitors must be very high to minimize the power dissipation generated by the internal esr, thereby improving system reliability and efficiency. the critical parameter is usually th e rms current rating, which must be higher than the rms input current. the maximum rms input current (flowing through the input capacitor) is: equation 17 where is the expected system efficiency, d is the duty cycle and i o is the output dc current. this function reaches its maximum value at d = 0.5 and the equivalent rms current is equal to i o divided by 2 (considering = 1). the maximum and minimum duty cycles are: equation 18 and equation 19 where v f is the freewheeling diode forward voltage and v sw the voltage drop across the internal pdmos. considering the range d min to d max , it is possible to determine the max. irms going through the input capacitor. capacitors that can be considered are: electrolytic capacitors: these are widely used due to t heir low price and their availa bility in a wide range of rms current ratings. the only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors. ceramic capacitors: if available for the required value and voltage rating, these capacitors usually have a higher rms current rating for a given physical dimension (due to very low esr). the drawback is the considerably high cost. i rms i o d 2d 2 ? -------------- - ? d 2 2 ------ - + ? = d max v out v f + v inmin v sw ? ------------------------------------ - = d min v out v f + v inmax v sw ? -------------------------------------- =
a5974ad application information doc id 018762 rev 1 25/49 tantalum capacitors: very good, small tantalum capacitors with very low esr are becoming more available. however, they can occasionally burn if subjected to very high current during charge therefore, it is better to avoid this type of capacitor for the input filter of the device. they can, however, be subjected to high surge current when connected to the power supply output capacitor the output capacitor is very important to meet the output voltage ripple requirement. using a small inductor value is useful to reduce the size of the choke but it increases the current ripple. so, to reduce the output voltage ripple, a low esr capacitor is required. nevertheless, the esr of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. if the zero goes to a very high frequency, its effect is negligible. for this reason, ceramic capacitors and very low esr capacitors in general should be avoided. tantalum and electrolytic capacitors are usua lly a good choice for this purpose. a list of some tantalum capacitor manufacturers is provided in ta b l e 7 . inductor the inductor value is very important as it fixes the ripple current flowing through the output capacitor. the ripple current is usually fixed at 20 - 40% of i omax , which is 0.6 - 1.2 a with i omax = 3 a. the approximate inductor value is obtained using the following formula: equation 20 table 6. list of ceramic capacitors for the a5974ad manufacturer series capacitor value ( ) rated voltage (v) taiyo yuden umk325bj106mm-t 10 50 murata grm42-2 x7r 475k 50 4.7 50 table 7. output capacitor selection manufacturer series cap value ( f) rated voltage (v) esr (m ) sanyo poscap (1) 1. poscap capacitors have some characterist ics which are very similar to tantalum. tae 47 to 680 2.5 to 10 25 to 35 tv 68 to 330 4 to 6.3 25 to 40 avx tps 100 to 470 4 to 35 50 to 200 kemet t494/5 100 to 470 4 to 20 30 to 200 sprague 595d 220 to 390 4 to 20 160 to 650 l v in v out ? () i ---------------------------------- t on ? =
application information a5974ad 26/49 doc id 018762 rev 1 where t on is the on time of the internal switch, given by d t. for example, with v out = 3.3 v, v in = 12 v and i o = 0.9 a, the inductor value is about 12 h. the peak current through the inductor is given by: equation 21 and it can be seen that, if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. so, when the peak current is fixed, a higher inductor value allows a higher value for the output current. in ta bl e 8 , some inductor manufacturers are listed. 8.2 layout considerations the layout of the switching dc-dc converters is very important to minimize noise and interference. power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. high impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as possible from the high current paths. a layout example is provided in figure 13 below. the input and output loops are minimized to avoid radiation and high frequency resonance problems. the feedback pin connections to the external divider are very close to the device to avoid pick-up noise. another important issue is the ground plane of the board. since the package has an exposed pad, it is very important to connect it to an extended ground plane in order to reduce the thermal resistance junction-to-ambient. table 8. inductor selection manufacturer series inductor value ( h) saturation current (a) coilcraft do3316t 5.6 to 12 3.5 to 4.7 coilcraft mss1260t 5.6 to 15 3.5 to 8 wurth elektronik we-pd l 4.7 to 27 3.55 to 6 i pk i o i 2 ----- + =
a5974ad application information doc id 018762 rev 1 27/49 figure 13. layout example 8.3 thermal considerations 8.3.1 thermal resistance r thj-a r thj-a is the equivalent static thermal resistance junction-to-ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. for this device, the path through the exposed pad is the one conducting the largest amount of heat. the static r thj-a measured on the application is about 40 c/w. the junction temperature of device is: equation 22 the dissipated power of the device is tied to three different sources: conduction losses due to the not insignificant r ds(on) , which are equal to: equation 23 where d is the duty cycle of the application. note that the duty cycle is theoretically given by the ratio between v out and v in , but in practice it is substant ially higher than this value to compensate for the losses in the overall application. for this reason, the switching losses related to the r ds(on) increases compared to an ideal case. switching losses due to turning on and off. these are derived using the following equation: equation 24 !-v !!$ t j t a r thja p tot ? + = p on r ds on () i out () ? 2 d ? = p sw v in i out t on t off + () 2 ----------------------------------- - f sw v in = i out t sw f sw ?? ? ??? =
application information a5974ad 28/49 doc id 018762 rev 1 where t rise and t fall represent the switching times of the power element that cause the switching losses when driving an inductive load (see figure 14 ). t sw is the equivalent switching time. figure 14. switching losses quiescent current losses. equation 25 where i q is the quiescent current. example: ?v in = 12 v ?v out = 3.3 v ?i out = 2a r ds(on) has a typical value of 0.25 @ 25 c and increases up to a maximum value of 0.5. @ 150 c. we can consider a value of 0.4 . t sw is approximately 70 ns. i q has a typical value of 5 ma @ v in = 12 v. the overall losses are: equation 26 the junction temperature of the device is: equation 27 p q v in i q ? = p tot r dson i out () ? 2 dv in i out t sw f sw v in i q = ? + ??? + ? = 0.4 2 2 0.3 12 2 70 10 9 ? 500 10 3 12510 3 ? ?? + ?? ? ? ? + ?? 1.38w ? = t j t a r thja p tot ? + =
a5974ad application information doc id 018762 rev 1 29/49 equation 28 8.3.2 thermal impedance z thj-a (t) the thermal impedance of the system, considered as the device in the hso8 package soldered on the application board, takes on an important rule when the maximum output power is limited by the static thermal performance and not by the electrical performance of the device. therefore, the embedded power elements could manage a higher current but the system is already taking away the maximum power generated by the internal losses. in case the output power increases, the thermal shutdown is triggered because the junction temperature triggers the designed thermal shutdown threshold. the r th is a static parameter of the package; it sets the maximum power loss which can be generated from the system given the operation conditions. if we suppose, as an example, t a = 80 c, 140 c is the maximum operating temperature before triggering the thermal shutdown and r th = 40 c/w, therefore, the maximum power loss achievable with the thermal performance of the system is: figure 15. represents the estimation of power losses for different output voltages at v in =5 v and t amb =80 c. the calculations are performed considering the r ds(on) of the power element equal to 0.4 a figure 15. power losses estimation (v in = 5 v, f sw = 500 khz) the red trace represents the maximum power which can be taken away, as calculated above, whilst the other traces are the total internal losses for different output voltage. the embedded condu ction losses are proportional to the duty cycle required for the conversion. assuming the input voltage constant, the switching losses are proportional to the output current while the quiescent losses can be considered as constant. as a consequence, in figure 15 , the maximum power loss is for v out =3.3 v, where the system can manage a continuous output current up to 1.8 a. the device could deliver a t j 60 1.38 42 128 c ? ? + = p max dc t r th ---------- - t j max t amb ? r th ------------------------------------- - 60 40 ------ 1.5w == ==
application information a5974ad 30/49 doc id 018762 rev 1 continuous output current up to 2 a to the load, however, the maximum power loss of 1.5 w is reached with an output current of 1.8 a, so the maximum output power is derated if t amb =80 c. figure 16 plots the power losses for v in =12 v and main output rails. figure 16. power losses estimation (v in = 12 v, f sw = 500 khz) at t amb =80 c and v in =12 v, the device is thermally limited only when v out =5 v (see figure 16 ). as a consequence, the calculation of the internal power losses must be done for each specific operating condition given by the final application. in applications where the current to the output is pulsed, the thermal impedance should be considered instead of the thermal resistance. the thermal impedance of the system could be much lower than the thermal resistance, which is a static parameter. as a consequenc e, the maximum power losses can be higher than 1.5 w if a pulsed output power is requested from the load: therefore, depending on the pulse duration and its frequency, the maximum output current can be delivered to the load. the characterization of the thermal impedance is strictly dependent on the layout of the board. in figure 17 the measurement of the thermal impedance of the demonstration board of the a5974ad is provided. p max t () t z th t () ---------------- - t j max t amb ? z th t () ------------------------------------- - ==
a5974ad application information doc id 018762 rev 1 31/49 figure 17. measurement of the thermal impedance of the demonstration board as can be seen, for example, for load pulses with a duration of 1 second, the actual thermal impedance is lower than 20 c/w. this means that, for short pulses, the device can deliver a higher output current value. 8.4 short-circuit protection in overcurrent protection mode, when the peak current reaches the current limit, the device reduces the t on down to its minimum value (approximately 250 nsec) and the switching frequency to approximately one third of its nominal value even when synchronized to an external signal (see section 5.4: current protection ). in these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to i lim . in any event, in case of heavy short-circuit at the output (v o = 0 v) and depending on the application conditions (v cc value and parasitic effect of external components), the current peak could reach values higher than i lim . this can be understood considering the inductor current ripple during the on and off phases: on phase equation 29 off phase equation 30 where v d is the voltage drop across the diode, dcr l is the series resistance of the inductor. in short-circuit conditions v out is negligible, so during t off the voltage across the inductor is very small, as equal to the voltage drop across parasitic components (typically the dcr of i l ton v in v out ? dcr l r ds(on) + () i ? ? l ------------------------------------------------------------------------------------- - t on () = i l toff v d v out dcr l i ? ++ () ? l -------------------------------------------------------------- t off () =
application information a5974ad 32/49 doc id 018762 rev 1 the inductor and the v fw of the free-wheeling diode) while during t on , the voltage applied to the inductor is instead maximized as approximately equal to v in . so, equation 29 and the 30 in overcurrent conditio ns can be simplified to: equation 31 considering t on , which has already been reduced to its minimum. equation 32 considering that f sw has already been reduced to one third of the nominal. in case a short-circuit at the output is applied, and v in = 12 v, the inductor current is controlled in most of the applications (see figure 18 ). when the application must sustain the short-circuit condition for an extended period, the external components (mainly the inductor and diode) must be selected based on this value. in case the v in is very high, it could occur that the ripple current during t off ( equation 32 ) does not compensate the current increase during t on ( equation 31 ). figure 20 shows an example of a power-up phase with v in = v in max = 36 v where il ton > il toff so the current escalates and the balance between equation 31 and 32 occurs at a current slightly higher than the current limit. this must be taken into account in particular to avoid the risk of an abrupt inductor saturation. figure 18. short-circuit current v in = 12 v i l ton v in dcr l r ds(on) + () i ? ? l ----------------------------------------------------------------- - t on min () v in l -------- - 250ns () ? = i l toff v d v out dcr l i ? ++ () ? l -------------------------------------------------------------- 3t ? sw () v d v out dcr l i ? ++ () ? l -------------------------------------------------------------- 12 s () ? =
a5974ad application information doc id 018762 rev 1 33/49 figure 19. short-circuit current v in = 24 v figure 20. short-circuit current v in = 36 v
application information a5974ad 34/49 doc id 018762 rev 1 8.5 application circuit figure 21 shows the demonstration board application circuit, where the input supply voltage, v cc , can range from 4 v to 36 v and the output voltage is adjustable from 1.235 v to 6.3 v due to the voltage rating of the output capacitor. figure 21. demonstration board application circuit !-v p& n& k table 9. component list reference part number description manufacturer c1 umk325bj106mm-t 10 f, 50 v taiyo yuden c2 68 nf, 5%, 0603 c3 150 pf, 5%, 0603 c4 22 nf, 5%, 0603 c10 poscap 6tvb330ml 330 f, 25 m sanyo r1 5.6 k , 1%, 0.1 w 0603 r2 3.3 k , 1%, 0.1 w 0603 r3 4.7 k , 1%, 0.1 w 0603 d1 stps3l40u 3 a, 40 v stmicroelectronics l1 mss1246t-123ml 12 h, i rms 20 c 3 a coilcraft
a5974ad application information doc id 018762 rev 1 35/49 figure 22. pcb layout (component side) figure 23. pcb layout (bottom side) figure 24. pcb layout (front side) !-v !-v !-v
application information a5974ad 36/49 doc id 018762 rev 1 8.6 positive buck-boost regulator the device can be used to implement a step-up/down converter with a positive output voltage. the output voltage is given by: equation 33 where the ideal duty cycle d for the buck-boost converter is: equation 34 however, due to power losses in the passive elem ents, the real duty cycle is always higher than this. the real value (that can be measured in the application) should be used in the following formulas. the peak current flowing in the embedded switch is: equation 35 while its average cu rrent is equal to: equation 36 this is due to the fact that the current flowing through the internal power switch is delivered to the output only during the off phase. the switch peak current must be lower than the minimum current limit of the overcurrent protection (see ta b l e 4 for details) while the average current must be lower than the rated dc current of the device. as a consequence, the maximum output current is: equation 37 where i sw max represents the rated current of the device. the current capability is reduced by the term (1-d) and so, for example, with a duty cycle of 0.5, and considering an average current through the switch of 2 a, the maximum output current deliverable to the load is 1 a. figure 25 below shows the circuit schematic of this topology for a 12 v output voltage and 5 v input. v out v in d 1d ? ------------- ? = d v out v in v out + ----------------------------- - = i sw i load 1d ? --------------- i ripple 2 ------------------- - + i load 1d ? --------------- v in 2l ? ---------- - d f sw --------- ? + == i sw i load 1d ? --------------- = i out max i sw max 1d ? () ? ?
a5974ad application information doc id 018762 rev 1 37/49 figure 25. positive buck-boost regulator 8.7 negative buck-boost regulator in figure 26 , the schematic circuit for a standard buck-boost topology is shown. the output voltage is: equation 38 where the ideal duty cycle d for the buck-boost converter is: equation 39 the considerations given in section 8.7 for the real duty cycle are still valid here. also equation 35 to 37 can be used to calculate the maximum output current. so, for example, considering the conversion v in = 12 v to v out = -5 v, i load = 0.5 a: equation 40 equation 41 an important point to take into account is that the ground pin of the device is connected to the negative output voltage. therefore, the device is subjected to a voltage equal to v in -v o , which must be lower than 36 v (the maximum operating input voltage). am09690v1 10v a5974ad 4.7 6. 8 6 470 e s r> 3 5m v out v in ? d 1d ? ------------- ? = d v ? out v in v out ? ----------------------------- - = d 5 512 + --------------- - 0.706 == i sw i load 1d ? --------------- 0.5 10.706 ? ----------------------- - 1.7a == =
application information a5974ad 38/49 doc id 018762 rev 1 figure 26. negative buck-boost regulator 8.8 floating boost current generator the a5974ad does not support a nominal boost conversion as this topology requires a low side switch, however, a floating boost can be useful in applications where the load can be floating. a typical example is a current generator for leds driving, as the led does not require a connection to the ground. figure 27. floating boost topology am09654v1 a5975ad 6 !-v
a5974ad application information doc id 018762 rev 1 39/49 figure 28. 350 ma led boost current source the device is powered from the output voltage so the maximum voltage drop across the leds and resistor sense is 36 v. the output voltage is given by: equation 42 where the ideal duty cycle d for the boost converter is: equation 43 as for positive and inverting buck-boost (see section 8.6 and section 8.7 ) the measured real duty cycle must be used to calculate the switch current level. the peak current flowing in the embedded switch is: equation 44 while its average cu rrent is equal to: equation 45 this is due to the fact that the current flowing through the internal power switch is delivered to the output only during the off phase. the switch peak current must be lower than the minimum current limit of the overcurrent protection (see ta b l e 4 for details) while the average current must be lower than the rated dc current of the device. !-v *1'vpdoovljqdo ,/(' p$ *1'srzhu 5vhqvh .=0x)9[ .=0x)9[ 9,1 9$& & 10 & 10 73 9$& 73 9$& & q & q 5 5 / x+ / x+ 5 . 5 . & q & q & x & x & 10 & 10 & x) & x) ' 6736/8 ' 6736/8 & q & q 73 9/(' 73 9/(' ' 6736/8 ' 6736/8 5 . 5 . ' 6736/8 ' 6736/8 & x & x 5 n 5 n ' 6736/8 ' 6736/8 73 9/(' 73 9/(' ' %=;& ' %=;& ' 6736/8 ' 6736/8 73 9'& 73 9'& 73 *1' 73 *1' 9287 9&& 95() (;3$' ,1+ &203 *1' )% 6<1& 8 /' 8 /' 73 9$& 73 9$& 5 5 4 %& 4 %& & x & x & x9 & x9 & 10 & 10 v out v in 1d ? ------------- = d v out v in ? v out ----------------------------- - = i sw i load 1d ? --------------- i ripple 2 ------------------- - + i load 1d ? --------------- v in 2l ? ---------- - d f sw --------- ? + == i sw i load 1d ? --------------- =
application information a5974ad 40/49 doc id 018762 rev 1 as a consequence, the maximum output current is: equation 46 where i sw max represents the rated current of the device. figure 28 shows a tested circuit to implement a boost current source for high current led driving (350 ma). to implement a boost conversion the led string must be composed of a minimum device number having a total voltage drop larger than maximum input voltage. the input voltage can be either dc or ac thanks to the input bridge rectifier. in the case of a dc voltage source d1, d2, d3, d4, c1, and c2 can be removed from the circuit and 1 f capacitor value can be used for c5. 8.9 synchronization example see section 5.3 for details. figure 29. synchronization example 8.10 compensation network with mlcc at the output the a5974ad standard compensation network (please refer to figure 1 and section 7 ) introduces a single zero and a low frequency pole in the system bandwidth, so a high esr output capacitor must be selected to compensate the 180-degree phase shift given by the lc double pole. the selection of the output capacitor must guarantee that the zero introduced by this component is inside the designed system bandwidth and close to the frequency of the double pole introduced by the lc filter. a general rule for the selection of this compound for the system stability is provided in equation 47 . equation 47 i out max i sw max 1d ? () ? ? am09655v1 a5974ad a5974ad f z esr 1 2 esr c out ?? ? ----------------------------------------------- - = bandwidth < f lc f < z esr 10 f lc ? <
a5974ad application information doc id 018762 rev 1 41/49 mlccs (multiple layer ceramic capacitor) with values in the range of 10 f-22 f and rated voltages in the range of 10 v-25 v are available today at relatively low cost from many manufacturers. these capacitors have very low esr values (a few m ) and are therefore occasionally used for the output filter in order to reduce the voltage ripple and the overall size of the application. however, the zero given by the output capacitor falls outside the designed bandwidth and so the system becomes unstable with the standard comp ensation network. figure 30 shows the type iii compensation netw ork stabilizing the system with ceramic capacitors at the output (the optimum components value depends on the application). this configuration introduces two zeroes and a low frequency pole in the designed bandwidth and so guarantees a proper phase margin. figure 30. mlcc compensation network circuit 8.11 external soft-start network at startup, the device can quickly increase the current up to the current limit in order to charge the output capacitor. if soft ramp-up of the output voltage is required, an external soft-start network can be implemented, as shown in figure 31 . the capacitor c is charged up to an external reference through r and the bjt clamps the comp pin. this clamps the duty cycle, limiting the slew rate of the output voltage. !-v 9729 vpdoovljqdo srzhusodqh *1' *1' & q) & q) &287 &287 5 . 5 . & q) & q) 5 10 5 10 5 5 9,1 9,1 & & & q) 9 & q) 9 ' 6736/8 ' 6736/8 5 5 9287 9287 & & *1' *1' & & 5 5 9287 9&& 95() (;3$' ,1+ &203 *1' )% 6<1& 5 5 & & & x) 9 & x) 9 / / 4 %& 4 %&
application information a5974ad 42/49 doc id 018762 rev 1 figure 31. soft-start network example !-v 9729 vpdoovljqdo srzhusodqh 73 *1' 73 *1' ' ' 4 %& 4 %& 5 . 5 . 73 9,1 73 9,1 & & 73 9287 73 9287 & & & q) & q) 73 *1' 73 *1' 9287 9&& 95() (;3$' ,1+ &203 *1' )% 6<1& 8 /[' 8 /[' / / & & 5 5 5 5 & 9 & 9 5 5
a5974ad typical characteristics doc id 018762 rev 1 43/49 9 typical characteristics figure 32. line regulator figure 33. shutdown current vs. junction temperature figure 34. output voltage vs. junction temperature figure 35. junction temperature vs. output current (v in = 5 v) figure 36. junction temperature vs. output current (v in = 12 v) figure 37. efficiency vs. output current (v in = 5 v) !-v 6 6 ?# ?# !-v !-v !-v ?x ??x ?x s /e ?sr ( ^t ?l,r >r, skhd?x?s skhd?x?s skhdx?s skhdx?s ?x x ?x ?x ??x ?x x x? x x? ?x s /e ?sr ( ^t ?l,r >r, skhd?x?s skhd?x?s skhdx?s skhdx?s
typical characteristics a5974ad 44/49 doc id 018762 rev 1 figure 38. efficiency vs. output current (v in = 12 v) !-v ?x ?x ??x ?x ??x s /e ?sr ( ^t ?l,r >r, skhd?s skhd?s skhd?x?s skhd?x?s x ?x x ?x ?x ??x ?x ??x x x? x x? ?x s /e ?sr ( ^t ?l,r >r, skhd?s skhd?s skhd?x?s skhd?x?s skhdx?s
a5974ad package mechanical data doc id 018762 rev 1 45/49 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions, and product status are available at: www.st.com . ecopack is an st trademark.
package mechanical data a5974ad 46/49 doc id 018762 rev 1 figure 39. package dimensions table 10. hsop8 mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.70 0.0669 a1 0.00 0.10 0.00 0.0039 a2 1.25 0.0492 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 d 4.80 4.90 5.00 0.1890 0.1929 0.1969 d1 3 3.1 3.2 0.118 0.122 0.126 e 5.80 6.00 6.20 0.2283 0.2441 e1 3.80 3.90 4.00 0.1496 0.1575 e2 2.31 2.41 2.51 0.091 0.095 0.099 e1.27 h 0.25 0.50 0.0098 0.0197 l 0.40 1.27 0.0157 0.0500 k0 (min), 8 (max) ccc 0.10 0.0039 $
a5974ad ordering information doc id 018762 rev 1 47/49 11 ordering information table 11. ordering information order codes package packaging a5974ad hsop8 tu b e A5974ADTR tape and reel
revision history a5974ad 48/49 doc id 018762 rev 1 12 revision history table 12. document revision history date revision changes 19-apr-2011 1 initial release
a5974ad doc id 018762 rev 1 49/49 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of A5974ADTR

	To Download A5974ADTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .